2013

Energy-efficient Sparse Matrix Autotuning with CSX - A Trade-off Study, Jan Christian Meyer, Juan Manuel Cebrian, Lasse Natvig, Vasileios Karakasis, Dimitris Siakavaras, and Konstantinos Nikas, to appear in proceedings of HP-PAC (High-Performance, Power-Aware Computing), to be presented at IPDPS in Boston 20 May 2013.

Energy-efficient Sparse Matrix Auto-tuning with CSX, Jan Christian Meyer,Lasse Natvig, Vasileios Karakasis, Dimitris Siakavaras, and Konstantinos Nikas, PRACE 2IP White paper, pdf

Power instrumentation of task-based applications using model-specific registers on the Sandy Bridge architecture, Jan Christian Meyer and Lasse Natvig, PRACE 2IP White paper, pdf

Challenges of reducing cycle-accurate simulation time for TBP applications, Alexandru C. Iordan, Magnus Jahre and Lasse Natvig, in proceedings of Int'l Conf. on Computational Science, ICCS 2013. Link

2012

Improving Energy Efficiency through Parallelization and Vectorization on Intel® Core i5-7 Processors, Juan M Cebrian, Lasse Natvig and Jan C Meyer, in proceedings of 5th Int'l Workshop on Multi-Core Computing Systems (MuCoCoS), Salt Lake City, Utah, November 16, 2012, in conjunction with the Supercomputing Conference (SC12). Link

Towards Efficient Simulation of Task Based Parallel Applications, Alexandru Iordan, Magnus Jahre and Lasse Natvig, In Proceedings of NIK'2012, PDF

Case Studies of Multi-core Energy Efficiency in Task Based Programs, Hallgeir Lien, Lasse Natvig, Abdullah Al Hasib, and Jan Christian Meyer, to appear in Proceedings of 2nd Int'l Conf. on ICT as Key Technology against Global Warming (ICT-GLOW 2012), A. Auweter et al. (Eds.): LNCS 7453, pp. 44–54. Springer, September 2012. (Springerlink)

Performance and Power Efficiency Analysis of Data Reuse Transformation Methodology on Multicore Processor, Abdullah Al Hasib, Per Gunnar Kjeldsberg, Lasse Natvig, to appear in proceedings of 1st Int'l Workshop on On-chip memory hierarchies and interconnects: organization, management and implementation, August 2012, in conjunction with Euro-Par 2012

IPM based sparse LP solver on a heterogeneous processor, Mujahed Eleyat and Lasse Natvig, Journal of Computational Management Science, Springer Verlag, accepted 4th January 2012. (Springerlink)

2011

Green Computing: Saving Energy by Throttling, Simplicity and Parallelization, Lasse Natvig and Alexandru Iordan, in CEPIS Upgrade magazine, special Issue on Green ICT, november 2011, PDF

Investigating the Potential of Energy-savings Using a Fine-grained Task Based Programming Model on Multi-cores, Alexandru Iordan (NTNU), Artur Podobas (KTH Royal Institute of Technology), Lasse Natvig (NTNU), Mats Brorsson (KTH Royal Institute of Technology), to appear in Proceedings of the 4th Workshop on Applications for Multi- and Many-Core Processors, A4MMC 2011

OpenCL acceleration of a Krylov solver library for finite element applications: Performance observations, Olav Fagerlund (The University of Tokyo), Hiroshi Okuda (The University of Tokyo, Okuda Laboratory), Lasse Natvig (NTNU), in Proceedings of 30th JSST Annual Conference (JSST 2011), Int'l Conf. on Modeling and Simulation Technology, 2011.

Cache-Aware Matrix Multiplication on Multicore Systems for IPM-based LP Solvers, Mujahed Eleyat, Lasse Natvig and Jørn Amundsen, Computer Aspects of Numerical Algorithms (CANA'11), Szczecin, Poland, September 2011

Parallel algorithms for the maximum fow problem with minimum lot sizes, Mujahed Eleyat, Dag Haugland, Magnus Lie Hetland and Lasse Natvig, Int'l conference on Operations Research OR'11, Zurich 2011.

The maximum flow problem with minimum lot sizes, Haugland,D., M.Eleyat, M.L.Hetland, in Lecture Notes in Computer Science, Vol. 6971, pp.170-182, 2011.

Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy, Marius Grannaes, Magnus Jahre and Lasse Natvig, ARCS 2011, 24th Int'l Conf. on Architecture of Computing Systems.

Storage Efficient Hardware Prefetching using Delta Correlating Prediction Tables, Marius Grannaes, Magnus Jahre, and Lasse Natvig, Journal of Instruction Level Parallelism (JILP), Volume 13, 2011.

2010

Managing Shared Resources in Chip Multiprocessor Memory Systems, Magnus Jahre, PhD Thesis, defended 12. October 2010.

Task Based Programming on Multicores, A Case Study on Energy Consumption, Alexandru Iordan, and Lasse Natvig, MultiCore Computing, MCC'10.

Mixed-Precision Parallel Linear Programming Solver, Mujahed Eleyat and Lasse Natvig, SBAC-PAD 2010, 22nd Int'l Symposium on Computer Architecture and High Performance Computing.

Energy Efficient Methods for Multi-Core Programming - Poster, Alexandru Iordan and Lasse Natvig, ACACES 2010 Summer School, Terrassa, Spain, July 2010.

Reducing Memory Latency by Improving Resource Utilization, PhD thesis by Marius Grannæs, defended 9th June 2010.

Multi-Level Hardware Prefetching using Low Complexity Delta Correlating Prediction Tables with Partial Matching, Marius Grannaes, Magnus Jahre, and Lasse Natvig, Transactions on High-Performance Embedded Architectures and Compilers, Volume 5, Issue 1, 2010.

Computational Computer Architecture Research at NTNU Magnus Jahre and Lasse Natvig, in ERCIM News 81.

Implementation of a Linear Programming Solver on the Cell BE Processor, Mujahed Eleyat and Lasse Natvig, International Conference on Computational Science, ICCS 2010, Amsterdam June 2010.

DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems , Magnus Jahre, Marius Grannas and Lasse Natvig. The 5th International Conference on High Performance and Embedded Architectures and Compilers 2010.

Multi-Level Hardware Prefetching using Low Complexity Delta Correlating Prediction Tables with Partial Matching, Marius Grannaes, Magnus Jahre and Lasse Natvig. The 5th International Conference on High Performance and Embedded Architectures and Compilers 2010. Nominated for best paper award

Agent-supported Programming of Multi-core Computing Systems, S. Pllana, S. Benkner, E. Mehofer, L. Natvig, and F. Xhafa. In 'Complex Intelligent Systems and Their Applications'. Published by Springer in the book series Springer Optimization and Its Applications. Volume 41, 207-224, DOI: 10.1007/978-1-4419-1636-5_10, 2010.

2009

A Quantitative Study of Memory System Interference in Future Chip Multiprocessor Architectures, Magnus Jahre, Marius Grannæs and Lasse Natvig, 11th IEEE International Conference on High Performance Computing and Communications (HPCC), June 25-27, 2009, Seoul, Korea.

A Light-Weight Fairness Mechanism for Chip Multiprocessor Memory Systems, Magnus Jahre and Lasse Natvig, ACM International Conference on Computing Frontiers, 2009.

A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors, Magnus Jahre and Lasse Natvig, In Transactions on High-Performance Embedded Architectures and Compilers, 2009. [ Paper ]

Storage Efficient Hardware Prefetching using Delta Correlating Prediction Tables, Marius Grannaes, Magnus Jahre and Lasse Natvig. Presented at 1st JILP Data Prefetching Championship, 2009. [ Paper, Presentation, All details, IDI-news ]

Towards an Intelligent Environment for Programming Multi-core Computing Systems, Sabri Pllana, Siegfried Benkner, Eduard Mehofer, Lasse Natvig, and Fatos Xhafa, Euro-Par 2008 Workshops, LNCS 5415, pp. 137–147, 2009.

Programming Graphics Processing Units (GPUs) MSc thesis by G.-R.Bakke in cooperation with ARM Norway,

Linear Programming on the Cell/BE MSc thesis by Åsmund Eldhuset in cooperation with Miriam AS.

Performance Study of Random Walk Simulations MSc thesis by Safurudin Mahic in cooperation with Numerical Rocks AS

2008

Low-Cost Open-Page Prefetch Scheduling in Chip Multiprocessors, Marius Grannaes, Magnus Jahre and Lasse Natvig, XXVI IEEE International Conference on Computer Design (ICCD), 2008.

2007

Architectural Techniques to Improve Cache Utilization, PhD thesis by Haakon Dybdahl (Now at Google).

Algorithmic and Scheduling Techniques for Heterogeneous and Distributed Computing, PhD thesis by Cyril Banino-Rokkones (Now at Yahoo Trondheim))

Performance Effects of a Cache Miss Handling Architecture in a Multi-core Processor, Magnus Jahre and Lasse Natvig, NIK 2007: Norwegian Informatics Conference, 2007.

An LRU-based Replacement Algorithm Augmented with Frequency of Access in Shared Chip-Multiprocessor Caches, Haakon Dybdahl, Per Stenström, and Lasse Natvig, SIGARCH Computer Architecture News 2007.

An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors, Haakon Dybdahl and Per Stenström, HPCA, 2007

2006

Master-slave tasking on asymmetric networks, Cyril Banino, Olivier Beaumont, Lasse Natvig, Euro-Par 2006, Lecture Notes in Computer Science Volum 4128. s. 167-176, 2006.

Cache Write-Back Schemes for Embedded Destructive-Read DRAM, Haakon Dybdahl, Marius Grannæs, and Lasse Natvig, Lecture Notes in Computer Science 3894 s. 145-159, 2006.

Destructive-Read in Embedded DRAM, Impact on Power Consumption, Dybdahl, Haakon; Per Gunnar Kjeldsberg, Marius Grannæs, and Lasse Natvig. Journal of Embedded Computing 2006.

A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors, Haakon Dybdahl, Per Stenström, and Lasse Natvig, Lecture Notes in Computer Science 2006, Volum 4297. s. 22-34, 2006.




2013/06/08 16:56, Lasse Natvig