EECS Seminar on Task Based Programming and Performance Predictability

NTNU, 19. May 2015, at 13:15h – 16:00 in Room 454 in the IT-building

https://research.idi.ntnu.no/multicore/seminar-2015

The computer architecture and design research group (CARD) at NTNU together with EECS will host a mini-seminar covering topics within Task Based Programming, load scheduling, multithreading and performance predictability at 19. May 2015. The seminar consists of four presentations and are open for all interested faculty members, students and industry. Contact person: Lasse Natvig, IDI.

Please sign up here http://doodle.com/4cvp2kc77ix33cz5 (for the waffles in the break)

Final programme

Abstracts for the presentations and presentation of the speakers are found below.

  • 13:15 – 14:00: Multi-core Research Topics Relevant to Automotive and Avionics Safety-critical Control Systems, by Prof. Dr. Theo Ungerer, University of Augsburg, Germany, slides
  • 14:00 – 14:30: Intel TBB: Lowering Overheads and Improving Energy Efficiency through Victim Selection Policies, by MSc Alexandru C Iordan, ARM Norway (Trondheim) slides paper
  • 14:30 – 14:40: short break, waffles & coffee
  • 14:40 – 15:10: Moving IO thread activation policies to user space using the kfutex mechanism, by PhD Helge Bahmann, Google Zurich, Switzerland. slides paper
  • 15:10 – 15:40: Linux Xenomai provides hard real-time for UAV sensor platform, MSc. Terje Frøysa, SINTEF, Trondheim. slides

Presentation abstracts

Theo Ungerer

Multi-core Research Topics Relevant to Automotive and Avionics Safety-critical Control Systems

Abstract: Utilisation of multi-cores in safety-critical systems in automotive and avionics domains is a hot research topic. Most researchers focus on mixed-criticality workloads developing hardware or software techniques for isolation of tasks among each other. The collaborative parMERASA project (Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability, funded by European Community, Oct. 1, 2011 until Sept. 30, 2014) investigated a timing analyzable system of parallel hard real-time applications running on a scalable multi-core processor. parMERASA targeted future complex control algorithms by parallelizing industrial hard real-time programs of automotive, avionics and construction machinery domains. Exchange of data between parallel tasks was required and therefore isolation had to be relaxed by predictable synchronisation techniques. The talk critically reflects the results of the parMERASA project and proposes research topics beyond the parMERASA project for embedded multi-core systems of near and far future.

Short Bio: Prof. Dr. Theo Ungerer received a Diploma in Mathematics at the Technical University of Berlin in 1981, a Doctoral Degree at the University of Augsburg in 1986, and a second Doctoral Degree (Habilitation) at the University of Augsburg in 1992. Ungerer was scientific assistant at the University of Augsburg , visiting assistant professor at the University of California, Irvine (1989-90), professor of computer architecture at the University of Jena (1992-1993) and the Technical University of Karlsruhe (1993-2001). Since April 2001 he is Chair of Systems and Networking at the University of Augsburg, Germany. He co-founded the HiPEAC Network of Excellence and coordinated the EC projects MERASA and parMERASA. The scientific interests of his research group at University of Augsburg concern multi-core design and system software of safety-critical systems, pattern-based parallelisation, transactional memory, and autonomic/organic distributed computing.

Terje Frøysa

Linux Xenomai provides hard real-time for UAV sensor platform

Abstract: Can an open source OS on an embedded COTS processor provide adequate responsiveness for an agile UAV? Despite the preemptive Linux kernel, hard real-time is hard to achieve. By introducing Xenomai and Adeos interrupt pipelining, hard real-time may seamlessly co-exist with a standard Debian Linux.

Short bio: Terje Frøysa is a research scientist at Sintef ICT since 1987 (dept. of Informatics and Communication Technology), and he was at Sintef Marintek in 1979 - 1987. He has over 35 years experience as HW/SW designer of embedded systems. He has a Bachelor degree Electronics and Programming, and a Master degree in Mathematics, Statistics and Radio Systems. He has experience in projects like Ocean laboratory instrumentation, Optical 6-deg high resolution position measurement systems, VME/VRTX based platform for sub-sea side-scanning sonar, HDTV terrestrial modem, Radar projects, Sub-sea umbilical modems, SIM-card with built-in Wi-Fi, and sensor systems for oil industry. His main research interests are Embedded software/hardware design and Real-time programming and FPGA design.

Helge Bahmann

Moving IO thread activation policies to user space using the kfutex mechanism

Abstract: kfutex present a mechanism for treating IO wake up notifications (and other kernel notifications) in the same way as inter-thread synchronization. This enables managing both in a unified fashion, and enables to mo ve thread activation policy decisions from kernel to user-space.

Short bio: Helge Bahmann is working as a Senior Software Engineer at Google Zürich since 2012. He received a diploma in mathematics at Freiberg University in 2002 and received a PhD in computer science in 2009. From 2009 to 2012 he worked at Secunet Security networks. He has vast engineering experience within the Linux environment (including but not limited to kernel, graphics stack, security systems) and been contributing to several projects. Research interests include operating systems, functional program representations and transformations, as well as formal verification via dependently typed programming.

Alexandru C Iordan

Intel TBB: Lowering Overheads and Improving Energy Efficiency through Victim Selection Policies

Abstract: The wide adoption of Chip Multiprocessors (CMPs) in almost all ICT segments has triggered a change in the way software needs to be developed. Parallel programming maximizes the performance and energy efficiency of CMPs, but also comes with a new set of challenges. One cost of parallel executions is the management overhead that can account for sub-linear speedups and can increase the energy consumption of applications. We break down Intel TBB’s parallelization overheads and report on how basic operations like task spawning, task stealing and task dequeuing impact the energy footprint. We also look into Intel TBB's victim selection policy. We implement three policies and compare them against the TBB's random approach: an “all knowing” oracle victim selection scheme, a pseudo-random approach and an occupancy-aware policy. This presentation reflects our results with all this research.

Short bio: Alexandru C. Iordan received his bachelor's and master's degrees at POLITEHNICA University of Bucharest. Afterwards he was granted a position in the CARD group at NTNU to do his PhD research under the supervision of Prof. Lasse Natvig. The focus of his work is improving energy-efficiency of multi-core platforms through parallelization.




2015/05/24 23:01, Lasse Natvig